The complexity of dealing with a BiCMOS process that makes use of CMOS and BJT devices is that CMOS devices have a voltage tolerance of 2.5, 3.0 and 3.5 V, while BJT's typically have a voltage tolerance of 5V.
In a modular approach it is desirable to use mask sets that will support both high voltage bipolar devices as well as low voltage CMOS devices.
One prior art solution makes use of a stacked CMOS arrangements to withstand the 5V power supply. In particular, in the prior art solution shown in FIG. 1, the ESD clamp 100 includes an RC timer 110, one embodiment of which is shown in greater detail in FIG. 2. The RC timer 110 in the FIG. 2 embodiment comprises a resistor 200 and a stacked arrangement of two poly capacitors 202, 204. The RC timer 110 generates two levels of triggering signals VTH and VTL to control a slave clamp driver, indicated generally by reference numeral 120. The RC timer 110 thus provides a high voltage trigger signal VTH and a low voltage trigger signal VTL feeding a PMOS-NMOS inverter. In particular, the RC timer trigger signals control the gates of a distributed PMOS stack defined by PMOS 122, 124 to support the 5V power supply across rails ESDP-ESDM. As in a non-stacked version the PMOS devices define an inverter by including NMOS 126. Thus the PMOS devices 122, 124 and NMOS 126 define a stacked inverter to accommodate the 5V bipolar voltage. The slave clamp driver 120, in addition to the stacked inverter, includes multiple stacked power NMOS devices 130, 132 (only one shown in FIG. 1), which define the NMOS clamp stack. These NMOS devices, making up the NMOS clamp stack are 3V devices. The stacked arrangement of the power NMOS devices 130, 132 thus defines a high voltage NMOS 130 (MNH) and a low voltage NMOS 132 (MNL) to accommodate the 5V bipolar voltage. In practice multiple pairs of the power NMOS clamp stacks are arranged in parallel to be able to handle the high ESD pulse currents. In order to ensure rapid turn-on of the NMOS clamp stacks (in this case, the stack defined by NMOS devices 130, 132) during an ESD pulse, to avoid gate voltage breakdown due to a breakdown voltage differential across the drain and gate of the NMOS devices, speed-up capacitors 140, 142 are provided across the drain and gate of the power NMOS devices 130, 132. The speed-up capacitors 140, 142 thus provide for rapid turn-on of the NMOS devices 130, 132 when the fast rise time ESD pulse is applied between the ESDP and ESDM buses.
After a delay time as defined by the time constant of the RC circuit 110, the trigger signals VTH, VTL go high and the output from the stacked inverter, pulls the gates of power NMOS devices 130, 132 low to turn off the MNH and MNL of the NMOS clamp stack to define a high impedance state. In contrast, the slow rise time power supply ramp when power is applied to the circuit, ensures that the capacitors of the RC-timer 110 have time to charge up, keeping the power NMOS devices 130, 132 in the off state.
In the circuit diagram of FIG. 1, the slave clamp 120 is depicted as comprising a single NMOS clamp stack defined by two power NMOS devices 130, 132, however in practice more than one NMOS clamp stack may be provided to handle the ESD current pulse. The problem is that NMOS devices are inherently large. Therefore, having to cascade multiple NMOS clamp stacks in parallel to handle the large ESD currents, results in a very large footprint ESD clamp.